// ram_rd.v


`timescale 1 ps / 1 ps
module ram_rd (
		input  wire        reset_reset_n,   // reset.reset_n
		input  wire        clk_clk,         //   clk.clk
		input  wire [9:0]  rd_2_address,    //  rd_2.address
		input  wire        rd_2_chipselect, //      .chipselect
		input  wire        rd_2_clken,      //      .clken
		output wire [15:0] rd_2_readdata,   //      .readdata
		input  wire        rd_2_write,      //      .write
		input  wire [15:0] rd_2_writedata,  //      .writedata
		input  wire [1:0]  rd_2_byteenable, //      .byteenable
		input  wire [9:0]  rd_1_address,    //  rd_1.address
		input  wire        rd_1_chipselect, //      .chipselect
		input  wire        rd_1_clken,      //      .clken
		output wire [15:0] rd_1_readdata,   //      .readdata
		input  wire        rd_1_write,      //      .write
		input  wire [15:0] rd_1_writedata,  //      .writedata
		input  wire [1:0]  rd_1_byteenable  //      .byteenable
	);

	wire    rst_controller_reset_out_reset; // rst_controller:reset_out -> [onchip_memory2_0:reset, onchip_memory2_1:reset]

	ram_rd_onchip_memory2_0 onchip_memory2_0 (
		.clk        (clk_clk),                        //   clk1.clk
		.address    (rd_1_address),                   //     s1.address
		.chipselect (rd_1_chipselect),                //       .chipselect
		.clken      (rd_1_clken),                     //       .clken
		.readdata   (rd_1_readdata),                  //       .readdata
		.write      (rd_1_write),                     //       .write
		.writedata  (rd_1_writedata),                 //       .writedata
		.byteenable (rd_1_byteenable),                //       .byteenable
		.reset      (rst_controller_reset_out_reset)  // reset1.reset
	);

	ram_rd_onchip_memory2_1 onchip_memory2_1 (
		.clk        (clk_clk),                        //   clk1.clk
		.address    (rd_2_address),                   //     s1.address
		.chipselect (rd_2_chipselect),                //       .chipselect
		.clken      (rd_2_clken),                     //       .clken
		.readdata   (rd_2_readdata),                  //       .readdata
		.write      (rd_2_write),                     //       .write
		.writedata  (rd_2_writedata),                 //       .writedata
		.byteenable (rd_2_byteenable),                //       .byteenable
		.reset      (rst_controller_reset_out_reset)  // reset1.reset
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~reset_reset_n),                 // reset_in0.reset
		.clk        (clk_clk),                        //       clk.clk
		.reset_out  (rst_controller_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                           // (terminated)
		.reset_in2  (1'b0),                           // (terminated)
		.reset_in3  (1'b0),                           // (terminated)
		.reset_in4  (1'b0),                           // (terminated)
		.reset_in5  (1'b0),                           // (terminated)
		.reset_in6  (1'b0),                           // (terminated)
		.reset_in7  (1'b0),                           // (terminated)
		.reset_in8  (1'b0),                           // (terminated)
		.reset_in9  (1'b0),                           // (terminated)
		.reset_in10 (1'b0),                           // (terminated)
		.reset_in11 (1'b0),                           // (terminated)
		.reset_in12 (1'b0),                           // (terminated)
		.reset_in13 (1'b0),                           // (terminated)
		.reset_in14 (1'b0),                           // (terminated)
		.reset_in15 (1'b0)                            // (terminated)
	);

endmodule
